This section only applies to 40G and 100G ports. For these ports an additional sub-tab will appear in the main Resource Properties tab as shown in the image below.
Ethernet at speeds of 40 and 100 Gbps uses the CAUI standard at Layer-1, the physical coding sub-layer. This divides the traffic into a number of physical lanes, which are transmitted together in various combinations depending on the interface type.
Within each lane the data is divided into 66-bit codewords which contain a 2-bit header. The data in each physical lane carries an alignment marker which contains the virtual lane number for this portion of the traffic.
Lanes may be physically swapped along the path from transmitter to receiver, and once the alignment markers are located inside each received lane the virtual lane numbers are used to put things in the right order. The lanes may also get skewed in time relative to each other during transit, and the alignment markers are also used to do the required de-skewing in the receiver.
On the transmit side, you can manually swap and skew the lanes as shown in the image to the right. You can also inject different kinds of CAUI errors into specific lanes as shown below.
Lane Status Monitoring
On the receive side, you can see whether there is proper header lock and alignment lock, and which virtual lane and actual skew is detected for each physical lane. You can also see which kind of CAUI errors are detected in each lane.
40/100G PRBS Testing
The physical lanes of a 40 or 100 Gbps port can also be put into PRBS mode, where they transmit a pseudo-random bit pattern which can be useful for testing physical cabling and connectors.
On the transmit side, you select whether each lane should be in PRBS mode, and also whether it should be subject to error injection:
Errors can be injected individually by clicking a button, or continuously by specifying a rate. Error injection also works for lanes that are not in PRBS mode, and can thus be used to simulate bit-level errors into the CAUI level.
On the receive side, you can see whether each physical lane has locked onto the PRBS pattern, and the number of bit errors while in PRBS lock: